The present invention relates to a power output stage.
In power output stages in ×DSL applications, powers of up to 100 mW frequently have to be transmitted from a switching centre to subscriber modems via conventional copper wire lines. The signal connection should take place with lower power dissipation and high linearity. At the same time, a corresponding output stage is arranged with other components in a very small space on a circuit board. To achieve the highest possible packing density, for example, a standard CMOS process is used which allows a maximum supply voltage of around 18V. The relatively high supply voltage is necessary for being able to transmit multi-tone signals with a high crest factor via the copper wire lines.
For example, D-type power stages are known which amplify relatively efficiently. To provide a general explanation of the problems involved, a corresponding class D power stage is shown in FIG. 1. Essentially, two transistors M1, M2 are driven as switches. The load paths or the controllable paths, respectively, of the transistors M1, M2 are connected between a supply voltage VDD−VSS. The corresponding gate terminals are in each case supplied with an input switching signal SIN, SINQ. The complementary switching signal SINQ is generated by an inverter I. At a node K between the controllable paths of the transistors M1, M2, an output signal OUT can be picked up which has a signal swing which corresponds to the supply voltage VDD−VSS. Furthermore, a diode D1, D2 are in each case provided which are connected in parallel with the controllable paths of the transistors M1, M2.
As a rule, the input switching signal SIN has a signal swing which corresponds to logic levels, for example of 2.5 V, whereas the supply voltage VDD−VSS can be about 20 V. The transistors M1, M2 must, therefore, exhibit particularly high electric strength. To construct such transistors with high voltage capability, a thick gate oxide and long channel lengths are therefore used in most cases. Furthermore, the transistors M1, M2 must permit high peak currents of up to some amperes so that the feedlines must be correspondingly dimensioned in the layout of a corresponding integrated chip and have relatively large distances from one another. The required drive with voltages of VDD/2 for the gate terminals, so that the corresponding transistor types can be operated efficiently as switches, is also disadvantageous. Accordingly, a driver stage must also be designed in such a manner that signal levels of VDD/2 can be generated. This results in further power dissipation and area requirement.
Corresponding power stages therefore have an increased requirement for area, among other things also because a large width-to-length ratio must be selected in order to achieve a low channel resistance of the transistors M1, M2. This then disadvantageously results in a large gate-source capacitance which is proportional to the gate area and which must be recharged during the switching process. This large capacitance then generates a high power dissipation which is proportional to the switching frequency of the supply voltage and the gate-source capacitance. Such simple class-D power stages are less suitable especially in ×DSL applications which are more and more widely used and which operate at switching frequencies around 20 MHz.
In published U.S.-application for patent No. 2004/0027755 A1, it is proposed to connect together a number of controllable paths of transistors to form a cascode arrangement. Although the electrical strength of the overall arrangement will be higher than that of the individual transistors it disadvantageously results in a high area requirement due to the many test code transistors. Furthermore, the channel resistances of the controllable paths add together to form a high resistance value which adversely affects the linearity of a corresponding power stage.